Right...
I think I have the files sorted now, but there may be a problem opening the files with the freeware version of Eagle as I think I've reached the board size limit.
I've managed to add the audio and video DAC now though. The problem is that I think I've reached the "board size" limit of the freeware version of Eagle, so you may need a "full" (hint) version of Eagle to be able to change the diagrams without problems.
Otherwise, if you try to move components around, Eagle might say something like "All your schematics are belong to us."!

If you've never heard of the "All your base" phenomenon, look here...
http://uk.youtube.com/watch?v=qItugh-fFgg
So, here's the fixed zip. I've used 20-1-09 as the date so it doesn't get confused with the old file. Please ignore the old file completely....
http://www.mediafire.com/?sharekey=6695 ... f6e8ebb871
@marshallh / all...
Yep, still here. The last time I spoke to you was when I started on the FPGA stuff, and I've been coding away / pulling my hair out ever since!
I did give thought to using the original N64 chips to debug things, but I think it would make the code far more complex than it needs to be. The thing is, the R4300 uses the "MIPS interface" protocol to communicate with the RCP - this is quite a complex protocol, and it would be easier to connect the CPU and RCP directly inside the FPGA code.
I'm aiming for 100% "functionally accurate", but not for 100% "physically accurate", since I also want to use DDR RAM anyway and get rid of the RDRAM. Certain features will be put in place to allow for easier expandability of the design (like hi-res textures etc.)
Actually, the biggest hurdle I'm having atm is how to connect the different blocks together. The original RCP has an internal high-speed bus, so it requires some sort of bus arbiter block to allow the processing blocks and CPU to share the same bus.
Until I can visualize a way of putting this together, I can't really proceed with things like the RSP and CPU cores....
I've used the Plasma MIPS core from opencores.org as a basis for the RSP, but I still haven't added the vector registers due to the above issues. Also, due to the way the Plasma core is coded (many separate "modules"), it would be easier to start from scratch and translate the MESS C++ RSP code into Verilog. The R4300 might as well be translated in this way too.
I'm using Altera Quartus as I also don't get on with the Xilinx ISE software (many people don't?). I don't think the Xilinx software is massively different, but the Altera software just appears a bit less fussy when compiling (Xilinx will often complain about every single error, while Quartus will still let me compile - although it still has tons of warnings.)
All I've managed so far is to decode the triangle commands and output the pixel coordinates. I have added the color combiner and texture unit, but it all needs some major testing.
I've also modded the MESS source slightly so it will dump the pixel coords from actual games so I can compare them to the Verilog simulation. At this stage, it's getting VERY difficult to test the texture unit stuff because I only have the basic RDP block done, and I need to dump the TMEM contents from a specific point in a real game to attempt to test the Verilog code.
If this sounds complicated, then keep in mind that I'm learning C++, Verilog, emulation etc. as I go along! It's already been a huge educational experience, but when things go wrong it's not much fun. I'm determined not to give up though.
All I'm looking forward to atm is actually seeing some polygons being drawn on a real monitor on a real FPGA. It should then be possible to stream the RDP command output from MESS into the FPGA via USB so the Verilog code can be debugged / improved until it displays the same thing that MESS does.
Incidentally, I've done a bit of tweaking to the MESS source in an attempt to implement some of the things which Mooglyguy has mentioned in his blog. I don't have the problem with the transparent "boxes" around sprites any more (eg. in Mario Kart), so that's good.
OzOnE.